Recently, an LSI comprising a high capacity memory element and a high performance logic element consolidated on a semiconductor substrate is highly demanded. In order to realize a high capacity memory element, a DRAM cell that has high compatibility with a formation process of the logic element and has a small area per unit is demanded. Particularly, a memory cell having a COB (capacitor over bit line) structure is demanded, which is capable of reducing the cell area by forming a capacitor on a bit line (hereinafter referred to BL). In order to realize a high performance logic element, for example, it is necessary to form a metal alloy represented by a salicide (self-aligned silicide) or to reduce the resistance of a diffusion layer by a metallic backing represented by a BMD (buried metal on diffusion layer).
An example of conventional process where the COB structure is employed and the resistance of the diffusion layer is reduced is described by referring to FIG. 1. (I) is a cross sectional view of a region where a memory element is formed (hereinafter referred to "cell region") along the line perpendicular to the BL, (II) is a cross sectional view of the cell region along the line perpendicular to a word line (hereinafter referred to WL (word line)), and (III) is a cross sectional view of a region where a logic element is formed (hereinafter referred to "logic region"). In the conventional process shown in FIG. 1, a trench element separating region 52, a gate electrode 53 and an insulating film pattern 54 are formed on a semiconductor substrate 51, and then a silicon nitride (Si.sub.3 N.sub.4) film 54 is formed on the whole surface of the semiconductor substrate 51. After the cell region is masked with a resist, a spacer side wall 55a composed of an Si.sub.3 N.sub.4 film 55 is formed on the side wall of the gate electrode 53 and the insulating film pattern 54 in the logic region, and at the same time, the surface of the semiconductor substrate 51 located at a diffusion layer 56 is exposed. A silicide layer 57 is then formed on the exposed surface of the semiconductor substrate 51.
While not shown in FIG. 1, formation of a contact part, a BL, and a lower electrode, an insulating film and an upper electrode of a capacitor is formed in the cell region. For example, the contact part may comprise a poly-Si plug, and the BL may comprise a stacked body of a tungsten silicide (WSi.sub.2) formed on a poly-Si layer. The lower and upper electrodes may comprise poly-Si, and the capacitor insulating film may comprise a silicon nitride (Si.sub.3 N.sub.4) film and a silicon oxide (SiO.sub.2) film.
In the process of forming the memory cell having the COB structure, a large step is formed between the cell region and the logic region due to the BL and the stacked capacitor. The margin in depth of focus (DOF) on lithography for forming an upper circuit over the cell region and the logic region is thus reduced, and processing of the circuit in the logic region becomes difficult. As a result, troubles such as etch residue on processing of the circuit arise to adversely affect the high integration of the logic element.
The formation of the poly-Si films for the BL and the lower and upper electrodes of the capacitor is generally conducted by a chemical vapor deposition (CVD) process. While the CVD process is generally conducted at about 600.degree. C., a heat treatment is required after formation of the film for the activation of the impurities contained in the poly-Si film. In the formation of the capacitor insulating film composed of an Si.sub.3 N.sub.4 film and an SiO.sub.2 film, a heat treatment is required, for example, at from about 850 to 900.degree. C. However, because the silicide layer formed in the logic region is low in heat resistance, it coagulates on the heat treatment to bring about deterioration in characteristics such as increase in resistance. Therefore, in the case where the silicide layer is formed to reduce the resistance of the diffusion layer, the heat treatment cannot be employed.
The formation process of the capacitor can be a low temperature process by employing an MIM (metal-insulator-metal) structure using a metal instead of the SIS (Si-insulator-Si) structure using the poly-Si. By substituting the conventional BL formed of a poly-Si film with a metal, it can be considered to conduct the BL formation process at a low temperature and to reduce the resistance of the BL.
However, it is unavoidable to use poly-Si for forming the contact part (particularly a memory node contact part connecting the lower electrode of the capacitor and the semiconductor substrate) because a metal deteriorating the junction leak is very difficult to be used. Furthermore, in a memory cell having the COB structure, a memory node contact part of poly-Si is formed after the formation of the BL since the capacitor is formed on the BL, and therefore the BL cannot be formed with a metal having a low melting point. As described in the foregoing, the compatibility between the formation process of the memory element and the formation process of the logic element is difficult to be realized because of the high barrier in the essential point.